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Examining Architectures for the Post-Exascale Era

As the train pulls into the Exascale station, researchers are starting to look beyond this impending milestone to the next technology breakthrough, realizing that current system architectures are not likely the path forward. Constraints surrounding materials and the realities of physics mean that the types of technological advances that have brought high performance computing technology to its present state are unlikely to continue without considerable changes being made.

We have nearly reached what appears to be the pinnacle of our current architectural paradigm, Exascale, at the infancy of artificial intelligence. Researchers are seeing scientific workloads becoming increasingly demanding, and the growth of these workloads only appears to be growing as we progress forward. To meet the scale of computing power needed for the applications of the future, researchers are looking towards entirely new system designs; enter Disaggregated Architectures.

What if we could enable system architects to decouple memory from processors and accelerators, and allow for flexible node designs that create the ability to re-architect a whole rack or whole row of racks on the fly to meet the demands of the current workload without having to worry about creating bottlenecks? Under the current technological regime, this is physically impossible – the challenge has always been that when you disaggregate resources, latency and the need for bandwidth increase dramatically. Faster interconnect, specifically in-package optical interconnect, is critical to improving and innovating this next generation architectural approach, and researchers are experimenting with them now.

Researchers have begun experimenting with disaggregated architectures that allow for flexible node designs in a production environment. Questions such as “Can in-package optical I/O provide a physical layer interconnect that allows various protocols to be overlaid on top of it in support of heterogenous connectivity?,” are being tested using high-ranking systems from the Top 500. Flexible system designs are being sampled and put through trials giving researchers the ability to examine new architectures and observe and analyze how they interact with different applications. How are these experiments going? What benefits are they finding? What drawbacks are they experiencing?

On Wednesday, November 11th, at 9am PST, a group of researchers and industry players on the leading edge of this new approach to HPC architecture join to explore the topic in a webinar titled, “Disaggregated System Architectures for Next Generation HPC and AI Workloads.”

Technology leaders representing the ecosystem to make these new architectures a reality will share their thoughts and experiences on a panel moderated by Timothy Pricket Morgan, including:

  • Doug Carmean, Architect at Microsoft
  • Dr. Josh Fryman, Senior Principal Engineer at Intel Corp
  • Dr. Ian Karlin, Principal HPC Strategist at Lawrence Livermore National Laboratory
  • John Shalf, Head for Computer Science at Lawrence Berkeley National Laboratory
  • Dr. Vladimir Stojanovic, Chief Architect at Ayar Labs and a Professor of EECS at UC Berkeley

Discussions will focus on the state of disaggregated architectures, including current challenges, new ways to design systems, and technologies that are needed to enable them for widespread use. This will include discussion on how emerging optical I/O technology is supporting heterogeneous connectivity with tremendous bandwidth and low latency, and the results that are coming from this approach to design.

Do not miss this opportunity to hear from the people on the cutting edge of emerging HPC architectures and the technologies that will support their development. Reserve your spot now, and hear about the next wave of architectures as they unfold in real time.

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